The present invention relates generally to semiconductor device processing techniques, and, more particularly, to a method for improving CMOS device performance by forming a self-aligned, dual silicon nitride liner.
Dual liner techniques have been introduced in order to provide different stresses in P-type MOS devices with respect to N-type MOS devices. For example, a nitride liner of a first type is formed over PFETs of a CMOS device, while a nitride liner of a second type is formed over the NFETs of the CMOS device. More specifically, it has been discovered that the application of a compressive stress in a PFET channel improves carrier mobility therein, while the application of a tensile stress in an NFET channel improves carrier mobility therein. Thus, the first type nitride liner over the PFET devices is formed in a manner so as to achieve a compressive stress, while the second type nitride liner over the NFET devices is formed in a manner so as to achieve a tensile stress.
For such CMOS devices employing dual liners, the conventional approach has been to form the two different nitrides using separate lithographic patterning steps. In other words, for example, the first type nitride liner is formed over both PFET and NFET devices, with the portions of the first type nitride liner over the NFET devices being thereafter patterned and removed. After an optional formation of an oxide layer, the second type nitride liner is formed over both regions, with a second patterning step being used to subsequently remove the portions of the second type nitride liner over the PFET devices. Unfortunately, due to inherent inaccuracies associated with aligning lithographic levels to previous levels, the formation of the two liners could result in a gap there between. This would in turn expose the underlying device layer to mobile ion degradation.
On the other hand, the two liners could also be formed in a manner such that one liner overlaps the other. In fact, the reticles used for the two separate patterning steps are typically designed to ensure an overlap such that there is no gap between the two liner materials. However, having certain regions with overlapping nitride liners creates other problems with subsequent processing due to issues such as reliability and layout inefficiencies. For example, a reactive ion etch (RIE) process for subsequent contact formation may have to accommodate for a single-thickness liner in some areas of the circuit, while also accommodating for a double-thickness (overlapping) liner in the interface areas. Moreover, if such overlapping areas are excluded from contact formation, a restriction results in terms of available layout area and critical dimension (CD) tolerances.
Accordingly, it would be desirable to be able to implement the formation of a dual liner CMOS device in a self-aligned manner that does not result in a gap between different liner types and/or an overlap thereof.